1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a phase locked delay circuit.
2. Description of the Related Art
A synchronous semiconductor memory device is provided with a clock buffer which receives an external system clock signal and converts the system clock signal to an internal clock signal needed for operating internal circuitry of the semiconductor chip such that internal clock signal is synchronized with the external system clock signal. A phase difference cannot be avoided between the external system and the internal clock signals. Researchers have worked to remove this phase difference by generating an internal clock in perfect synchronization with an external system clock signal.
One approach developed to minimize the phase difference between external system clock CLK and internal clock PCLK involves using a phase locked loop (PLL) circuit. A second approach involves using a delay locked loop (DLL) circuit.
The operation of a PLL synchronizing circuit will be explained below with reference to FIG. 1. The PLL circuit shown in FIG. 1 comprises a phase detector 12, a loop filter 14, and a voltage controlled oscillator 16. When external system clock CLK and internal clock PCLK are applied to phase detector 12, it detects the phase difference and supplies a phase difference detection signal to loop filter 14. Loop filter 14 is a low-pass filter which generates a direct current control voltage V(t) by filtering the phase difference detection signal. Loop filter 14 supplies control voltage V(t) to voltage controlled oscillator 16 connected, in turn, to the output port. Voltage controlled oscillator 16 generates internal clock PCLK having a frequency corresponding to the level of control voltage V(t) output from loop filter 14.
Consequently, if the phase difference between external system clock CLK and internal clock PCLK has a positive value, control voltage V(t) is increased. By doing so, the cycle of internal clock PCLK output from voltage controlled oscillator 16 is reduced, and thus the phase difference between external system clock CLK and internal clock PCLK is reduced. On the other hand, if the phase difference between the external clock CLK and internal clock PCLK has a negative value, control voltage V(t) is decreased resulting in an increase in the cycle of internal clock PCLK output from voltage controlled oscillator 16 and a decrease in the phase difference between external system clock CLK and internal clock PCLK.
The operation of a DLL synchronizing circuit is similar to that described above. In the case of a DLL circuit, voltage controlled oscillator 16 is replaced by a voltage controlled delay circuit. The delay produced by the voltage controlled delay circuit varies according to control voltage V(t).
Using PLL and DLL synchronizing circuits to synchronize an internal clock signal to an external clock signal has several drawbacks. The locking time, i.e., the time required to synchronize the internal clock PCLK with the external system clock CLK, is long. Increased locking time results in increased data access time, and thus, slower acquisition times. Additionally, the synchronizing circuit must be operated at all times and during all device states, including standby, increasing the standby current and the consequent power consumption.
Another approach to reduce clock skew between an external and an internal clock signal is to employ a voltage controlled delay line. The circuit typical of this approach is the synchronous delay line (SDL) disclosed in U.S. Pat. No. 4,975,605 entitled SYNCHRONOUS DELAY LINE WITH AUTOMATIC RESET to Mel Bazes, issued Dec. 4, 1990. Typical improvements on the synchronous delay line circuit are the synchronous mirror delay (SMD) and a hierarchical phase locking delay (HPLD) circuits employed in 256M DRAMs.
Use of an SMD circuit brings about the same result. The SMD circuit controls connections between forward mirror-shaped unit delays and backward unit delays only with a mirror-shaped control circuit including, for example, NAND gates, to thereby realize phase synchronization. Therefore, the SMD circuit, although overcoming variations dependent on temperature and process, lengthens the delay line of forward and backward mirror-shaped unit delays resulting in an increased layout area of the semiconductor chip.
Therefore a need remains for a circuit for synchronizing an internal clock signal to an external clock signal which reduces locking time, power consumption, and layout area.